%% Abstract for
%% Pierre Salverda's MSc Research Reportn
%% An SRAM Main Memory Model. Final version February 1998

\chapter*{Abstract}

A growing gap between CPU and DRAM performance is driving processors
further away from their peak execution rates by increasing the amount
of time spent waiting for the memory system.  To date, cache memories
have been used to good effect in offsetting lagging DRAM speeds by
buffering frequently referenced instructions and data near the CPU.
However, continued increases in the cost of DRAM accesses call for
improvements in cache performance, and in particular, that of the
secondary cache.  More specifically, strategies which target the
secondary cache hit rate for improvement are becoming increasingly
important, even if they result in an increase in the cost of each
miss.

This research examines a proposed new organization for the memory
hierarchy in which main memory is implemented in SRAM (replacing the
secondary cache), and the role of DRAM is relegated to that of a
paging device.  In this model, called the \textit{RAMpage memory
  hierarchy}, a software-managed paging system takes the place of the
traditional, hardware-implemented block placement and replacement
strategies used by the secondary cache.  Effectively, full
associativity is provided for in SRAM, and this occurs at no
additional cost or cycle time penalties to the hardware.  Moreover,
treating the secondary cache as main memory facilitates pinning of
critical operating system code and data in that level, further
reducing the total number of references which reach DRAM.  Working
against these benefits, however, is the increase in the cost of an
SRAM miss (now called a page fault), which results from the invocation
of memory management software to retrieve the missing information from
DRAM.

Trace-driven simulation is used to evaluate the performance of the
RAMpage hierarchy.  The results presented in this research indicate a
reduction of between 40 and 90\% in the total number of references to
DRAM, and these are shown to amortize the additional overheads
incurred by the paging software required to achieve them.  Scalability
of the RAMpage hierarchy is also demonstrated through the extent to
which an increasing CPU-DRAM gap causes its performance to degrade
relative to that of a conventional memory hierarchy.  Overall,
reductions of between 3 and 17\% in total simulation time are achieved
by the new hierarchy.

While a more detailed analysis of the RAMpage hierarchy is called for,
the preliminary simulation results presented here indicate good
potential for its overall success.  This research therefore
demonstrates that the RAMpage hierarchy represents a feasible
alternative to conventional organizations of the memory hierarchy, and
more importantly, one which will become increasingly attractive as the
gap between CPU and DRAM speeds continues to widen.