Further Cache and TLB Investigation of the RAMpage Memory Hierarchy

Philip Machanick and Zunaid Patel

The RAMpage memory hierarchy is an alternative to the traditional
division between cache and main memory: main memory is moved up a
level and DRAM is used as a paging device.  Earlier RAMpage work has
shown that the RAMpage model scales up better with the growing
CPU-DRAM speed gap, especially when context switches are taken on
misses.  This paper investigates the effect of more aggressive
first-level (L1) cache and translation lookaside buffer (TLB)
implementations, with other parameters kept the same as in previous
work, to illustrate that a more aggressive design improves the
competitiveness of RAMpage.  The more aggressive L1 shows an increase
in the advantage or RAMpage with context switches on misses,
supporting the hypotheses that a more aggressive L1 favours RAMpage. 
However, results without context switches on misses are less conclusive. 
A larger TLB, as predicted, makes RAMpage viable over a wider range of
page sizes.