Scalability of the RAMpage Memory Hierarchy
Philip Machanick
Department of Computer Science
University of the Witwatersrand

The RAMpage memory hierarchy is an alternative to the traditional 
division between cache and main memory: main memory is moved 
up a level and DRAM is used as a paging device.  As the CPU-DRAM speed 
gap grows, it is expected that the RAMpage approach should become more 
viable. Results in this paper show that RAMpage scales better than a 
standard second-level cache, because the number of DRAM references is 
lower. Further, RAMpage allows the possibility of taking a context 
switch on a miss, which is shown to further improve scalability. The 
paper also suggests that memory wall work ought to include the TLB, 
which can represent a significant fraction of execution time.