Correction to RAMpage ASPLOS Paper
Philip Machanick
Department of Computer Science
University of the Witwatersrand
2050 Wits, South Africa
philip@cs.wits.ac.za

This paper contains corrections to published results on the RAMpage memory 
hierarchy.  The originally published results contained erroneous values for 
cache miss penalties for a conventional cache architecture against which 
the RAMpage hierarchy was being compared.  The incorrect results showed 
that RAMpage with context switches on misses to DRAM had similar 
performance to a conventional 2-way associative L2 cache-based hierarchy.  
The corrected results show that the RAMpage hierarchy in fact outperforms a 
conventional 2-way associative cache hierarchy by up to 29%, for the 
measured variations.